/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2023-2024, Phytium Technology Co., Ltd.
 * Phytium pe2201 boards information header.
 */

#ifndef __BOARD_H_
#define __BOARD_H_
#include <linux/delay.h>

/*******************************early setup smc id*****************************/
#define CPU_SVC_VERSION                         0xC2000F00
#define CPU_GET_RST_SOURCE                      0xC2000F01
#define CPU_INIT_PLL                            0xC2000F02
#define CPU_INIT_PCIE                           0xC2000F03
#define CPU_INIT_MEM                            0xC2000F04
#define CPU_INIT_SEC_SVC                        0xC2000F05
#define CPU_SECURITY_CFG                        0xC2000F07
#define CPU_GET_MEM_INFO                        0xC2000F14

#define SET_PHY_MODE                            0xC2000015
#define SET_SMMU_DOMAIN                         0xC2000F09

/*******************************parameter check*******************************/
#define PARAMETER_CPU_MAGIC                     0x54460020
#define PARAMETER_COMMON_MAGIC                  0x54460013
#define PARAMETER_PLL_MAGIC                     0x54460020
#define PARAMETER_PCIE_MAGIC                    0x54460021
#define PARAMETER_MCU_MAGIC                     0x54460024
#define PARAMETER_BOARD_MAGIC                   0x54460015
#define PARAMETER_PAD_MAGIC                     0x54460016

/*******************************default PEU set*******************************/
#define CONFIG_PCI_PEU0                         0x1

/*0x0: disable peu1, 0x01: enable peu1 */
#define CONFIG_PCI_PEU1                         0x1

/*0:single		1：multiple*/
#define CFG_INDEPENDENT_TREE                    0x0

/* peu */
#define X4                                      0x0
#define X2X1X1                                  0x1
#define X1X1X1X1                                0X2

/*peu_psu*/
#define X1X1                                    0x0
#define X0X1                                    0x1
#define	X1X0                                    0x2
#define X0X0                                    0x3
#define PEU_PSU_C0                              0x31000000
#define LPI_CTR_COUNTER3                        0x98
#define CONFIG_PEU_PSU_C0                       0x80b4

#define CONFIG_PEU0_SPLIT_MODE                  X4
#define CONFIG_PEU1_SPLIT_MODE                  X1X1

/* peu device mode: 0 ep, 1 rc default */
#define PCI_PEU0                                0x1
#define PCI_PEU1                                0x1
#define PEU1_OFFSET                             16
#define PEU_C_OFFSET_MODE                       16
#define PEU_C_OFFSET_SPEED                      0
#define EP_MODE                                 0x0
#define RC_MODE                                 0x1

#define GEN3                                    3
#define GEN2                                    2
#define GEN1                                    1

#define GPIO_RESET_PCIE                         0

/**************************************LSD***********************************/
#define LSD_BASE                                0x2807e000
#define CREG_LSD_RST_CONFIG3                    0x0c

/*******************************sgmii training*******************************/
#ifdef PHYTIUM_ETH_TRAIN
#define TRAINING_RX_DESC                        0x80000000
#define TRAINING_TX_DESC                        0x80100000
#define TRAINING_TX_BUFFER                      0x80200000
#define TRAINING_RX_BUFFER                      0x80300000
#define BUFFER0_OFFSET                          0x000
#define BUFFER1_OFFSET                          0x080
#define BUFFER2_OFFSET                          0x100
#define BUFFER3_OFFSET                          0x180

/* ETH register offsets */
#define FT_NCR                                  0x0000 //Network Control
#define FT_CFG                                  0x0004 //Network Config
#define FT_NSR                                  0x0008 //Network Status
#define FT_DMA_CFG                              0x0010 //DMA Configuration
#define FT_MAN                                  0x0034 //PHY Maintance
#define FT_FRAMES_TXED_OK                       0x0108 //The correct number of packets to be sent
#define FT_FRAMES_RXED_OK                       0x0158 //The correct number of packets to recv
#define FT_FCS_ERRORS                           0x0190 //Packet check sequence
#define FT_RX_SYMBOL_ERRORS                     0x0198 //The number of packets received  when the rx_er is valid

/* Bit manipulation macros */
#define FT_BIT(name)                            (1 << FT_##name##_OFFSET)
#define FT_BF(name, value)                      (((value) & ((1 << FT_##name##_SIZE) - 1)) \
                                                 << FT_##name##_OFFSET)
#define FT_BFEXT(name, value)                   (((value) >> FT_##name##_OFFSET) \
                                                 & ((1 << FT_##name##_SIZE) - 1))

/* Bitfileds in NCR */
#define FT_MPE_OFFSET                           4 //Management port enable
#define FT_MPE_SIZE                             1

/* Bitfields in MAN */
#define FT_DATA_OFFSET                          0 //data
#define FT_DATA_SIZE                            16
#define FT_CODE_OFFSET                          16 //Must be written to 10
#define FT_CODE_SIZE                            2
#define FT_REGA_OFFSET                          18 //Register address
#define FT_REGA_SIZE                            5
#define FT_PHYA_OFFSET                          23 //PHY address
#define FT_PHYA_SIZE                            5
#define FT_RW_OFFSET                            28 //Operation, 10 is read, 01 is write
#define FT_RW_SIZE                              2
#define FT_SOF_OFFSET                           30 //Must be written to 1 for Clause 22
#define FT_SOF_SIZE                             2

/* Bitfields in NSR */
#define FT_IDLE_OFFSET                          2 //The PHY management logic is idle
#define FT_IDLE_SIZE                            1

/* Register access macros */
#define ft_just_readl(port, reg)                readl(port + FT_##reg)
#define ft_just_writel(port, reg, value)        writel((value), (port) + FT_##reg)

#define RECEIVE_Q_PTR                           0x0018 //0 queues are prohibited
#define TRANSMIT_Q_PTR                          0x001c //0 queues are prohibited
#define INT_ENABLE                              0x0028 //Interrupt Enable
#define UPPER_RX_Q_BASE_ADDR                    0x04d4 //Used when 64-bit addressing is enabled
#define UPPER_TX_Q_BASE_ADDR                    0x04c8 //Used when 64-bit addressing is enabled
#define PCS_CONTROL                             0x0200 //BITs[12]:Enable auto-negotiation
#endif

#ifdef PHYTIUM_ETH_TRAIN
void phytium_eth_training(void);
#endif

#ifdef PHYTIUM_PINCTRL_TOOLS
int pe2201_pin_ctrl(void);
#endif

#ifdef PHYTIUM_SAVE_TRAIN_DATA
void save_train_data(void);
#endif

void check_reset(void);
void pll_init(void);
void pe2201_ddr_init(uint32_t s3_flag);
int pe2201_phy_init(void);

uint16_t i2c_read_spd_lmu_freq(uint8_t ch_enable);
void sec_init(uint8_t s3_flag);
void pcie_init(void);
void register_pfdi(void);
void core_security_level_cfg(void);

void gsd_sata_setup(void);
void psu_sata_setup(void);
void usb_init_setup(void);
void vhub_init_setup(void);
void onewire_init_setup(void);
void gpio_reset_device(int dev_id, int level);
void mio_func_sel(void);
void bmc_init(void);

/*****************************************SCMI*************************************/
#define SCMI_CH_STATUS_RES0_MASK                        0xFFFFFFFE
#define SCMI_CH_STATUS_FREE_SHIFT                       0
#define SCMI_CH_STATUS_FREE_WIDTH                       1
#define SCMI_CH_STATUS_FREE_MASK                        ((1 << SCMI_CH_STATUS_FREE_WIDTH) - 1)

#define SCMI_MAX_PARM_CPUNT                             10
#define MBX_UBOOT_SCP_CHN                               1

#define SCMI_IS_CHANNEL_FREE(status)                    \
        (!!(((status) >> SCMI_CH_STATUS_FREE_SHIFT) & SCMI_CH_STATUS_FREE_MASK))

#define SCMI_MARK_CHANNEL_BUSY(status)                  \
        do {                                            \
            (status) &= ~(SCMI_CH_STATUS_FREE_MASK << SCMI_CH_STATUS_FREE_SHIFT); \
        } while (0);

#define SCMI_MSG_CREATE_E(_protocol, _msg_id, _token)   \
	 ((((_protocol) & 0xff) << 10) |                    \
	 (((_msg_id) & 0xff) << 0) |                        \
	 (((_token) & 0x3ff) << 18))

typedef struct mailbox_mem_e {
	unsigned int res_a;		/* Reserved */

	volatile unsigned int status;
	unsigned long res_b;	/* Reserved */
	unsigned int flags;
	volatile unsigned int len;
	unsigned int msg_header;
	unsigned int payload[];
} mailbox_mem_e_t;

void scmi_bmc_jpeg_reset_delay(void);
void bmc_smmu_setup(void);
void bmc_heart_beat(void);
void bmc_clear_jpeg_int(void);

#endif
